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10s–16s Battery Pack Reference Design With Accurate Cell Measurement and High-Side MOSFET Control

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ESD Performance The ESD performance of this design was tested in a TI lab per IEC 61000 - 4 - 2. Isolated DC source and resister divider are used to simulate battery pack. Only ESD contact discharge was tested and the test results are listed in Table 3-6. Table 3-6. ESD Performance Voltage Applied Terminal PACK+ PACK– 2 kV PASS PASS –2 kV PASS PASS 4 kV PASS PASS –4 kV PASS PASS 8 kV PASS PASS –8 kV PASS PASS www.ti.com Hardware, Software, Testing Requirements, and Test Results TIDUEY5 – JANUARY 2021 Submit Document Feedback 10s–16s Battery Pack Reference Design With Accurate Cell Measurement and High-Side MOSFET Control 17 Copyright © 2021 Texas Instruments Incorporated

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